The present invention relates to a memory device; and, more particularly, to a memory device that can detect a mismatch in a bit line sense amp amplifying a potential difference between a pair of bit lines.
Basically, a memory device reads and writes data required by external devices. A basic unit for storing data is called a “cell,” and the memory device has one capacitor for storing one data. In order to read the data stored in the capacitor and to accurately transfer it outside, it is necessary to accurately decide polarity of data stored in the cell. To this end, the memory device is provided with a bit line sense amp as a device for deciding/amplifying data.
FIG. 1 is a circuit diagram for describing the concept of a cell array and a bit line sense amp according to the prior art. Word lines (WL1, WL2 and WL3), bit line separation signals(BISH and BISL) and a bit line equalization signal BLEQ are illustrated in FIG. 1.
Normally, a pair of bit lines BL and /BL connected to the bit line sense amp is precharged to a same voltage level. Then, when a first word line WL1 is enabled, a cell transistor 101 connected to the first word line WL is turned on, and data charged in a capacitor 102 flows through a channel of the cell transistor 101 to the bit line BL (this is called “charge sharing”). At this time, the negative bit line /BL maintains the precharge voltage VBLP level, and only an electric potential on the positive bit line BL is changed through charge sharing.
On the other hand, as well-known in the art, the bit line sense amp 103 serves to recognize a potential difference between both ends of the positive bit line BL and the negative bit line /BL, and to fully amplify a high electric potential to an even higher electric potential and to fully amplify a low electric potential to an even lower electric potential (this is also called “sensing”).
Ideally, the bit line sense amp 103 should be able to accurately sense even a small potential difference between both ends of the bit line pair BL and /BL, and amplify it. However, this is not so in reality. A potential difference dV(delta V) between both ends of the bit line pair BL and /BL enough to do the sensing operation is called an offset voltage of the bit line sense amp. If the potential difference between both ends of the bit line pair BL and /BL is not higher than the offset voltage, it is not guaranteed that the bit line sense amp 103 could perform an accurate sensing operation. One of the factors that cause such an offset voltage is a mismatch in the bit line sense amp 103. That is, a latch PMOS pair and a latch NMOS pair in the bit line sense amp 103 responsible for sensing should be fabricated identically as cross-coupled pairs, but their layout is not exactly symmetric in reality. Also, even if the layout is symmetric somehow, their patterns are not formed identically. In addition, a contact is not always defined in the same way. Because of these problems, a mismatch inevitably exists in the bit line sense amp 103.
FIG. 2 is a block diagram illustrating a bit line sense amp and a sense amp drive unit according to the prior art.
The sense amp drive unit 210 has a role of controlling the bit line sense amp 220 to start and stop sensing in response to an external command, and is provided with a sense amp controller 230 and a sense amp driver 240. A power-up signal PWEUP, a precharge pulse PCGP, a bit line equalization signal BLEQ, bit line pairs (BL u, /BL u, BL d and /BL d) and bit line separation signals(BISH and BISL) are illustrated in FIG. 2.
FIG. 3 shows a detailed circuit diagram of the sense amp controller 230 according to the prior art.
The sense amp controller 230 is a part that applies a pull-up drive signal RTOEN and a pull-down drive signal SBEN to the sense amp driver 240 in response to signals provided from outside. Its operation will now be explained with reference to FIG. 3.
When an Active command is inputted and an active pulse ACTP goes HIGH, the active pulse ACTP is inverted by an inverter I1. Then, a LOW voltage is fed to the gate of a transistor P1, so that the transistor P1 is turned on and a node a becomes a HIGH state. The HIGH voltage at the node a is latched and inverted by inverters I3 and I4 having input and output terminals interlocked to each other, thereby making a voltage at a node b in a LOW state. Further, the voltage of the node b is inverted by each of inverters I5 and I6, so that the pull-up drive signal RTOEN and the pull-down signal SBEN are outputted at HIGH states, respectively.
Thereafter, when a precharge command is inputted and a precharge pulse PCGP goes HIGH, the transistor N1 is turned on, the node a becomes a LOW state, and the pull-up drive signal RTOEN and the pull-down drive signal SBEN become a LOW state, respectively.
In FIG. 3, a power-up signal PWRUP is a signal for keeping initial values of the pull-up drive signal RTOEN and of the pull-down drive signal SBEN in LOW states; delay circuits 301 and 302 and switches connected thereto are for controlling a start time of the pull-up drive signal RTOEN and the pull-down drive signal SBEN. These signals are not necessarily related to the present invention. An external voltage VDD, a ground voltage VSS, and a transistor N2 are illustrated in FIG. 3.
FIG. 4 provides a detailed circuit diagram of the sense amp driver 240 according to the prior art.
The sense amp driver 240 serves to receive the pull-up drive signal RTOEN and the pull-down drive signal SBEN from the sense amp controller 230, and supply a pull-up drive voltage RTO and a pull-down drive voltage SB to the bit line sense amp 220. And, a core voltage VCORE is illustrated in FIG. 4. An operation thereof will now be described with reference to FIG. 4.
During the precharge operation, a Bit Line EQualizing (BLEQ) signal becomes a HIGH state, and makes the RTO and SB nodes to a bit line precharge voltage VBLP. However, when the Active command is inputted, the BLEG signal becomes a LOW state. In result, the RTO and SB nodes are separated from each other; and when the signals RTOEN and the SBEN are inputted from the sense amp controller 230, the transistors T1 and T2 are turned on and the RTO node becomes a core voltage VCORE while the SB node become a ground voltage, to thereby drive the bit line sense amp 220.
As described above, because the conventional sense amp drive unit 210 simultaneously feeds the pull-up drive voltage RTO and the pull-down drive voltage SB to the bit line sense amp 220 during an active operation, a sensing operation occurs simultaneously by the NMOS transistor pair and the PMOS transistor pair in the bit line sense amp 220. Therefore, if an error occurs during a read operation, it is hard to find out whether the error is caused by a mismatch in the NMOS transistors or by a mismatch in the PMOS transistors.